Responsibilities include development of test environments and tests to enable functional verification of large, multi-million gate ASICs. Additional responsibilities include verification plan development, code coverage analysis, formal equivalency checking, and behavioral modeling. The qualified candidate will be knowledgeable in Verilog and/or VHDL, C/C++, Java, or other programming languages. The qualified candidate will be knowledgeable in industry-standard simulators (VCS, MTI, NC-Verilog), gate-level simulation techniques, and logic debug. Additional experience with formal verification tools, hardware design and debug, constrained-random verification techniques, and System Verilog is a plus.

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2026 Software Dev Engineer Intern - Germany